Apparatus and method for uniformly performing comparison operations on long word operands

ABSTRACT

Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly such that it represents the result of the whole multi-word subtraction until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to computing, and more particularly, to a method, system, and apparatus for uniformly performing comparison operations on operands represented by more than one machine word. More specifically, the invention describes a new computer instruction that is used for performing long word comparison operations.

[0003] 2. Description of Prior Art

[0004] Many popular CPU's, such as the Intel IA32 family, the SPARC™ processor from Sun Microsystems, Inc., the Power PC from IBM, and the Alpha processor from Digital Equipment Corporation, each have their own instruction set. When a programmer wishes to write a program to be executed by a particular CPU, the programmer composes the program from the corresponding instruction set. To run the program, the instructions are converted into machine instructions that are then executed by the CPU in program order.

[0005] Integer values are stored as words in the registers of the CPU whose size is defined by the particular CPU architecture. For example, in a 32-bit machine architecture, the word size is 32 bits. The registers in such a machine are therefore 32 bits wide.

[0006] The execution of an ADD or SUB instruction at the machine level is relatively straightforward. The corresponding bit positions of the two registers defined by the instruction are added or subtracted bit by bit from the least significant bit (LSB) to the most significant bit (MSB). Instruction sets also include a type of instruction generally called a conditional branch. With these types of instructions, execution typically continues at a new address which is specified with the conditional branch if the condition is met. If the condition is not met, execution usually continues with the next instruction in program order. A conditional branch tests if a particular condition occurred by analyzing certain flags. Typically, most CPUs store these certain flags in what is commonly referred to as the condition code register (CC register). CC registers usually hold a multitude of different flags, including but not exclusive, the sign flag S, the overflow/underflow flag V, the carry/borrow flag C, and the zero flag Z. Different conditional branches test for different conditions by checking for different flags to be set/cleared in the condition code register. For example, a conditional branch testing for the “is zero” condition will test if the Z flag is set in the CC register at the time of the execution of the conditional branch. If the Z flag is set in the CC register, the conditional branch will continue at the new address, otherwise it will continue with the next instruction in program order.

[0007] The flags in condition code registers can be set via a multitude of ways. However, most CPUs automatically set the flags in the CC register according to the result of the previous instruction. For example, most CPUs have an ADD or SUB instruction that adds or subtracts the integer values stored in two registers, and then stores the result in one of the two or a third register. Usually, the ADD or SUB instruction will also update the flags in the CC register such that the status of the flags reflect the outcome of the result. For example, if the result after ADD or SUB is zero, the Z flag will be set in the CC register. Similarly, whenever a carry or borrow occurs, a carry flag C is set so that the hardware performing the addition or subtraction can take the carry or borrow condition into account for the next MSBs. One problem with addition or subtraction is that the sum or difference of the two integer operands may be too large or small to be represented in a 32-bit wide register. This event is called overflow with addition and underflow with subtraction. When an overflow/underflow condition occurs, an underflow/overflow flag V is set to indicate that the sum or difference of the two operands is too large or small to be represented in the register.

[0008] Usually, an ADD or SUB instruction (and many other instructions, for that matter) followed by a conditional branch instruction can be used together to control the execution of the program depending on the relation between two integer values. For example, if a conditional branch should occur depending on whether two integer values X1 and X2 are the same, the necessary instruction sequence would look as follows for many CPUs: First, the values of X1 and X2 are moved into corresponding registers R1 and R2. Then, a SUB instruction is used to subtract R2 from R1, and store the result in either R1, R2 or another register R3. The SUB instruction will also set the CC register's flags depending on the result of the subtraction. If both X1 and X2 are the same, the result will be zero, otherwise it will not be zero. The Z flag in the CC register will be set automatically by the SUB instruction if the result is zero, otherwise it will be cleared. Thus, if and only if the Z flag is set in the CC register, X1 and X2 are the same. Therefore, a conditional branch testing the Z flag can be used to change the flow of a program depending on whether the two operands X1 and X2 are the same or not.

[0009] Because comparison of two integer values is a very important operation, most CPUs provide a special compare instruction CMP for that purpose. Such a CMP instruction usually behaves exactly like a SUB instruction, except that it does not store the result of the subtraction in one of the two or a third register. But like the SUB instruction, a CMP instruction updates the flags in the CC register. Thus, the CMP instruction is specially made to just subtract two integer values and update the CC accordingly, but discards the actual result. The advantage of the CMP instruction is that no register is changed to hold the result of the subtraction operation. Thus, the CMP instruction simply updates the flags in the CC register depending on the relation between the two integer values. A CMP instruction is usually followed by a conditional branch which tests the flags for a particular condition, depending on the relation that needs to be tested. In this way, conditional branches testing the CC flags can be used to change the flow of a program depending on the result of the comparison operation of the two operands.

[0010] It should be noted that the CMP instruction is helpful but not necessary, and that it can always be replaced with a SUB instruction if an extra unused register is available to store the result. For that reason and to not unnecessarily obscure the scope of the present invention, in the following we will not use CMP, but SUB instead. Table 1 below provides a listing of the relationship between certain relations for unsigned and two's complement (i.e., signed) integer arithmetic and their corresponding flag settings. It suffices to say that most instruction sets provide conditional branch instructions testing the CC flags for conditions corresponding to the following relations: equal (=), not equal (!=), less than (<), less than or equal (<=), greater than (>), or greater than or equal (>=). It should also be noted that the conditions to be tested for these relations are different for signed (two's complement) and unsigned integer arithmetic. TABLE I DESCRIPTION DESCRIPTION RELATION FLAGS (Two's Complement) FLAGS (Unsigned) = Z If the Z flag is set, Z If the Z flag is set, indicating that the indicating that the difference between the difference between the compared operands is zero, compared operands is zero, the condition is met. the condition is met. ≠ not Z If the Z flag is not set, it not Z If the Z flag is not set, it indicates the compared indicates the compared operands are not the same operands are not the same and the condition is met. and the condition is met. < S ≠ V If the S flag is set but there C If the carry flag C is set, is no overflow, it indicated then the condition is met. that the result of the subtraction is negative and the condition is met. ≦ S ≠ V This condition is met if the C or Z If the carry flag C or the or Z S and V flags are not the zero flag Z is set, then the same as described above condition is met. with regard to the (<) relation or if the Z flag is set indicating the two operands are the same. > S = V This condition is met if S Not C If both the carry flag C and and not and V are both set and not the zero flag Z are not set, Z indicating that the Z then the condition is met. difference is positive and Z is not set indicating that the values are not the same. ≧ S = V This condition is met if Not C If the carry flag C is not both the S and V flags are set, then the condition is set met

[0011] In this way, a conditional branch testing the CC flags can be used to change the control flow of a program depending upon the result of the comparison operation of the two operands. However, many programming languages, such as JAVA, Smalltalk, and C++, and the like, support arithmetic operations and comparisons of integer values more than one machine word wide. For example, a long integer in the JAVA programming language is 64-bits wide and therefore requires two words in a 32-bit machine (such as would be required in an Intel X86 architecture) to be represented. In other languages like Smalltalk, integer values can be arbitrarily long and thus may require multiple words to be represented.

[0012] As described above, comparing two 1-word integers essentially requires the subtraction of the two 1-word integers with a SUB instruction. The SUB instruction in turn will set the flags in the CC register accordingly and, if desired, a conditional branch testing the CC register flags can be used to change the program flow depending on the outcome of the comparison. Consequently, comparing two n-word integers (where n is greater than or equal to 1) should be done in the same way as is 1-word integers, by subtracting the two n-word integers and testing the CC register flags afterwards. For example, a 64 bit word D₁ can be stored in two 32 bit registers (R₁ and R₂) in a 32 bit machine as shown in FIG. 1. Using the arrangement shown in FIG. 1, the register R₂ stores the least significant 32 bits of the 64 bit data word D₁ as a least significant word (LSW) D_(1L) while the register R₁ is used to store the most significant 32 bits as a most significant word (MSW) D_(1H). Similarly, a 64 bit word D₂ can be stored in two 32 bit registers (R₃ and R₄) where the register R₃ stores the 32 bit LSW of the 64 bit data word D₂ (i.e; D_(2L)) and the register R₄ is used to store the 32 bit MSW of the 64 bit data word D₂ (i.e; D_(2H)).

[0013] As described above, the CC flags S, Z, V, and C are the flags tested by conditional branches for the six primitive compare operations (<, >, =, ≠, ≦, ≧). The S flag depends only on the sign of the result (which is the most significant bit in a 2's complement representation), while the V flag indicates internal carry for the second most significant bit to the most significant bit of the result, and the C flag indicates carry to or borrow from the next word. Since the S, V, and C flags depend only on the operation applied and result obtained for the most significant word of an n-word integer, the S, V, and C flags are correctly set for both 1 and n-word subtractions using either a conventional SBB (subtraction with borrow) or a SUB operation. In order, therefore, to compare the n-word data words D₁ and D₂, the LSWs of each data word (i.e., D_(1L) and D_(2L)) and the MSWs (i.e., D_(1H) and D_(2H)) of each data word are subtracted from each other using what is referred to as a subtraction (SUB) without borrow instruction and a subtraction with borrow (SBB) instruction. It should be noted that the first subtraction uses the SUB operation since the first subtraction needs to set the Z flag based upon the result of the subtraction and ignore the C flag. Also, it should be noted that the SBB instruction is working like the SUB instruction, but that it additionally takes into account the state of the C flag for the subtraction (in which case the C flag indicates “borrow”).

[0014] Unfortunately, however, the Z flag depends on all bits of an integer and if the integer is represented by more than one data word, information about the bits of all words must be comprehended in the computation. Since the subtraction of two n-word integers requires n subtractions starting with the least significant word, and since the SBB operation sets the Z flag only according to the result of the most recent SBB operation, the conditional operations that require testing of the Z flag (i.e., >, ≦, ≠, and =) will not work properly. For example, using the comparison of long data words D₁ and D₂, the result of the SBB operation on the MSWs of D₁ and D₂ will be the only result comprehended in the state of the Z flag regardless of the results of previous SBB operations for the lower order words.

[0015] Therefore, in order for multi-word comparison to be a uniform extension of the single-word comparison, what is required is a subtraction operation that maintains information about all the bits in comparing two n-word integers.

SUMMARY OF THE INVENTION

[0016] The invention relates to a method, apparatus and system for comparing a first multi-word operand with a second multi-word operand. In one embodiment, the first multi-word operand is formed of n words (where n is greater than or equal to 1) hierarchically arranged from a first operand lowest order word (LSW) to a first operand highest order word (MSW) while the second operand is formed of n words hierarchically arranged from a second operand lowest order word (LSW) to a second operand highest order word (MSW).

[0017] As a method, using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero (Z) flag is cleared such that a Z flag status is not set. If, however, the result of the subtracting is zero, then the Z flag is set as usual. Next, a first operand next higher order word is subtracted from a second operand next higher order word using a subtraction with borrow and a sticky not Z flag (SBBZ) instruction and, based upon the subtracting, the Z flag is updated accordingly until the first operand highest order word is subtracted from the second operand highest order word. The comparing of the first operand and the second operand is then based upon the Z flag status, if needed, after the subtraction of the first operand highest order word is subtracted from the second operand highest order word. In this way, the method can be used for comparing the multi-word width operands of any conditional branch instruction which defines one of the following relations: equal (=); not equal (≠); less than (<); less than or equal (≦); greater than (>); or greater than or equal (≧).

[0018] In another embodiment, a CPU configured to execute a machine instruction requiring a comparison of two multi-word operands for execution is described. The CPU includes a zero (Z) flag, subtraction circuitry configured to perform a subtraction operation on each of the words of the two multi-word operands respectively, and reset circuitry configured to reset the Z flag such that a Z flag status is not set if any of the subtraction operations on the two multi-word operands is not zero.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, wherein like reference numerals refer to analogous or similar elements to facilitate ease of understanding.

[0020]FIG. 1 shows an exemplary multi-word integer.

[0021]FIG. 2 is a block diagram of a CPU capable of executing the subtraction instruction for long words in accordance with the present invention.

[0022]FIG. 3 is a logic diagram of circuitry in the CPU used to implement the subtraction instruction of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known structures or operations have not been described in detail in order to not unnecessarily obscure the invention.

[0024] All modern computing architectures provide what is referred to as a subtraction without borrow (SUB) as well as a subtraction with borrow (SBB) instruction that are used to set a condition code register to any of a number of condition code (CC) flags which is used for conditional branches. These condition flags are the sign (S) flag, the overflow/underflow (V) flag, the carry (C) flag, and the zero (Z) flag. In the described embodiment, the S flag depends only on the sign of the result (which is the most significant bit in a 2's complement representation), the V flag indicates internal carry for the second most significant bit to the most significant bit of the result, the C flag indicates carry or borrow for the next word, while the zero flag Z signifies if the difference between the compared operands is zero. Since the S, V, and C flags depend only on the operation applied and result obtained for the most significant word (MSW) of an n-word integer, these condition codes are correct for both 1 and n word integers using the conventional SBB instruction. Since, however, the conventional SBB instruction sets the Z flag only according to the result of the last and most recent subtraction operation, the conditional operations that depend on the Z flag status for the whole multiword subtraction (i.e., >, ≦, ≠, and =) are not correct.

[0025] Therefore, the invention corrects this problem by establishing a new subtraction instruction referred to as subtraction with borrow and sticky not Z flag, or more simply, SBBZ. In the described embodiment, the SBBZ instruction provides that the Z flag is updated based upon the following conditions:

[0026] 1) if the result of the SBBZ instruction is not zero, then the Z flag is cleared (i.e., the Z flag status is “not set”);

[0027] 2) in all other cases the Z flag is not changed.

[0028] In this way, once the Z flag is cleared, it remains cleared (i.e., the “not Z” information is “sticky” in that it flows through bits of the computation regardless of the number n of words used to represent an integer). It should be noted that the SBBZ instruction can be used in a manner substantially the same as the conventional SBB instruction except, unlike the SBB instruction, if during the subtraction steps of the SBBZ instruction, if any one of the n word results are not zero, the Z flag is cleared.

[0029] The invention will now be described in terms of a digital computing system. However, it should be noted, that the inventive subtraction instruction can be used in any system where comparison of multiple word integers in any suitable representation is used.

[0030] Referring to FIG. 2, a block diagram of a CPU 10 capable of uniformly performing comparisons of multi-word length operands by using an SBBZ instruction is shown. The CPU 10 includes an algorithmic unit (ALU) 12, a register file 14 including a plurality of registers R₁ through R_(n−1), multiplexer 16, and a CC register 18. During operation, the instructions of a program are executed in the ALU 12. Just prior to execution, any source register values needed by an instruction are ascertained and fetched by the multiplexer 16 from the register file 14. The instruction is then executed and the result is provided to a destination register in the register file 14 by the multiplexor 16.

[0031] During a comparison operation in which the CPU 10 uses a subtraction without borrow (SUB) instruction for a first word subtraction and the SBBZ instruction thereafter, the Z flag is cleared (i.e., status is “not set”) if any of the results indicates that the compared words are not equal, otherwise the Z flag remains unchanged. The Z flag therefore is set only if the whole result (and thus each SUB result) is equal to zero.

[0032] Operation of the SBBZ instruction is best described using an example. Consider the subtraction of two n-word integers X and Y (where n is greater than or equal to 1). The n-word integers X and Y can be represented as:

X=X_(n−1), X_(n−2) . . . X₁, X₀

Y=Y_(n−1), Y_(n−2) . . . Y₁, Y₀;

[0033] where (X₀,Y₀) and (X_(n−1), Y_(n−1)) are the least significant word (LSW) and most significant word (MSW), respectively of the integers X and Y.

[0034] During execution, the least significant words (X₀, and Y₀) are first subtracted (using a subtraction without borrow instruction). If the two operands (X₀ and Y₀) are the same, meaning the difference equals zero, then the value of the Z flag is set. If, they are not equal, the Z flag is reset. The next higher order words (X₁, and Y₁), are then compared using the inventive SBBZ instruction which is repeated for each pair of words until X_(n−1) and Y_(n−1) are subtracted. The following subtraction instructions represent the machine sequence required to perform the compare of the multi-word operands X and Y in accordance with the present invention (note that some CPUs require a third register to be specified to hold the result of each individual SUB or SBBZ instruction—since we are only interested in the final setting of the CC register flags, these extra register specifications have been left out for simplicity): SUB X₀,Y₀ SBBZ X₁,Y₁    SBBZ X_(n−1)Y_(n−1) (where n ≧ 1)

[0035] When the most significant words (i.e., X_(n−1)Y_(n−1)) are subtracted, the C, S and V flags are set, respectively, based upon the carry, sign and overflow/underflow conditions of the final subtraction result. The Z flag is based upon the subtraction results of all the subtractions performed for all n words and not (as with the conventional SBB or SUB instruction) only on the subtraction result of the MSW. In this way, any non-zero result is carried through (i.e., the sticky nature of the Z flag) and is comprehended in the condition code represented by the Z flag such that all condition codes based upon the Z flag are correct.

[0036] A particular example using decimal representation of integers is shown in Table III.

[0037] In the example shown in Table II, an integer X is represented as the decimal integer (73421095) with “5” being the LSW and “7” being the MSW. In a similar way, an integer Y is represented as the decimal integer (73420095) with “5” being the LSW and “7” being the MSW. The comparison operation between X and Y proceeds from the LSW to the MSW with the result determining the status of the Z flag as shown. As can be seen, the Z flag is set until the respective comparison results in a non-zero result at which time the Z flag is reset (i.e., the Z flag status is “not set”). Since all subsequent subtractions result in a zero result, the Z flag status remains “not set” thereby carrying this Z flag status through to the MSW subtraction result which results in the conditional operations that require testing of the Z flag status (i.e., >, ≦, ≠, and =) to be correct. Table III also shows a second example where the integer Y is now represented by the decimal integer (73220095) illustrating that even if subsequent subtractions result in a non-zero result, the not Z flag remains “sticky” throughout. TABLE II X 7 3 4 2 1 0 9 5 Y 7 3 4 2 0 0 9 5 Z Not Z Not Z Not Z Not Z Not Z Z Z Z X 7 3 4 2 1 0 9 5 Y 7 3 2 2 0 0 9 5 Z Not Z Not Z Not Z Not Z Not Z Z Z Z

[0038]FIG. 3 illustrates a typical, general-purpose computer system suitable for implementing the present invention. The computer system 330 includes at least one processor 332 (also referred to as a central processing unit, or CPU) that is coupled to memory devices including primary storage devices 336 (typically a read only memory, or ROM) and primary storage devices 334 (typically a random access memory, or RAM).

[0039] Computer system 330 or, more specifically, CPUs 332, may be arranged to support a virtual machine, as will be appreciated by those skilled in the art. One example of a virtual machine that may be supported on computer system 330 will be described below with reference to FIG. 3. As is well known in the art, ROM acts to transfer data and instructions uni-directionally to the CPUs 332, while RAM is used typically to transfer data and instructions in a bi-directional manner. CPUs 332 may generally include any number of processors. Both primary storage devices 334, 336 may include any suitable computer-readable media. A secondary storage medium 338, which is typically a mass memory device, is also coupled bi-directionally to CPUs 332 and provides additional data storage capacity. The mass memory device 338 is a computer-readable medium that may be used to store programs including computer code, data, and the like. Typically, mass memory device 338 is a storage medium such as a hard disk or a tape which generally slower than primary storage devices 334, 336. Mass memory storage device 338 may take the form of a magnetic or paper tape reader or some other well-known device. It will be appreciated that the information retained within the mass memory device 338, may, in appropriate cases, be incorporated in standard fashion as part of RAM 336 as virtual memory. A specific primary storage device 334 such as a CD-ROM may also pass data uni-directionally to the CPUs 332.

[0040] CPUs 332 are also coupled to one or more input/output devices 1040 that may include, but are not limited to, devices such as video monitors, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, or other well-known input devices such as, of course, other computers. Finally, CPUs 332 optionally may be coupled to a computer or telecommunications network, e.g., an internet network or an intranet network, using a network connection as shown generally at 1012. With such a network connection, it is contemplated that the CPUs 332 might receive information from the network, or might output information to the network in the course of performing the above-described method steps. Such information, which is often represented as a sequence of instructions to be executed using CPUs 332, may be received from and outputted to the network, for example, in the form of a computer data signal embodied in a carrier wave. The above-described devices and materials will be familiar to those of skill in the computer hardware and software arts.

[0041] In accordance with various embodiments of the invention, an n-word subtraction using the SBBZ instruction can be followed by any conditional branch instruction which requires the status of the Z flag to determine if the condition defined by the comparison is met. For example, any processor having an instruction set that defines one or more conditional branches based on the relations: equal (=); not equal (≠); less than (<); less than or equal (≦); greater than (>); or greater than or equal (≧) and requires the status of the Z flag as listed in Table II can take advantage of the SBBZ instruction of the present invention.

[0042] While the invention has been described in relationship to the to the embodiments shown and described herein, other alternatives, embodiments, and modifications will be apparent to those skilled in the art. It is intended that the specification be only exemplary, and that the true scope and spirit of the invention be indicated by the following claims. 

What is claimed is:
 1. A method of comparing a first operand and a second operand, wherein the first operand is formed of n words where n is greater than or equal to 1 and the second operand is formed of n words wherein both the first operand is hierarchically arranged from a first operand lowest order word (LSW) to a first operand highest order word (MSW) and wherein the second operand is hierarchically arranged from a second operand lowest order word (LSW) to a second operand highest order word (MSW), comprising: (a) subtracting the first operand lowest order word from a second operand lowest order word; (b) if the result of the subtracting (a) is not zero, then clearing a zero (Z) flag such that a Z flag status is not set; (c) if the result of the subtracting (a) is zero, then setting the Z flag such that the Z flag status is set; (d) subtracting a first operand next higher order word from a second operand next higher order word; (e) if the result of the subtracting (d) is not zero, then clearing the zero (Z) flag such that the Z flag status is not set; and (f) repeating (d)-(e) until the first operand highest order word is subtracted from the second operand highest order word.
 2. A method as recited in claim 1, wherein the first operand and the second operand are each integers.
 3. A method as recited in claim 2, wherein the comparing is followed by a conditional branch operation performed by a central processing unit (CPU).
 4. A method as recited in claim 3, wherein the conditional branch is selected from a group testing for any of the following conditions: equal (=); not equal (≠); less than (<); less than or equal (≦); greater than (>); or greater than or equal (≧).
 5. A CPU configured to execute a machine instruction requiring a comparison of two multi-word operands for execution comprising: a zero (Z) flag; subtraction circuitry configured to perform a subtraction operation on each of the words of the two multi-word operands respectively; and reset circuitry configured to reset the Z flag such that a Z flag status is not set if any of the subtraction operations on the two multi-word operands is not zero.
 6. The CPU of claim 5, wherein the reset circuitry is further configured to not reset the Z flag if all of the subtraction operations on the two multi-word operands are zero.
 7. The CPU of claim 5, wherein the subtraction circuitry is further configured to successively subtract the words of the multi-length operands from the least significant words to the most significant words.
 8. The CPU of claim 5, wherein a SUBZ result is generated for each subtraction operation performed by the subtraction circuitry on the words of the multi-word operands.
 9. The CPU of claim 3, wherein once the Z flag has been reset, the reset circuitry is further configured to maintain the Z flag in the reset state even if subsequent subtractions of the words of the multi-length operands result in a difference of zero.
 10. The CPU of claim 5, wherein the machine instruction defines a conditional branch instruction.
 11. The CPU of claim 10, further comprising circuitry to ascertain if the condition defined by the conditional branch instruction is met by analyzing the value of the Z flag after the subtraction circuitry performs the subtraction operation on each of the words of the two multi-word operands.
 12. The CPU of claim 11, wherein the conditional branch instruction defines one of the following relations: equal (=); not equal (≠); less than (<); less than or equal (≦); greater than (>); or greater than or equal (≧).
 13. A method of providing a CPU configured to execute a machine instruction requiring a comparison of two multi-word operands for execution comprising: providing a zero (Z) flag; providing subtraction circuitry configured to perform a subtraction operation on each of the words of the two multi-word operands respectively; and providing reset circuitry configured to reset the Z flag such that a Z flag status is not set if any of the subtraction operations on the two multi-word operands is not zero.
 14. The method of claim 13, wherein the step of providing the reset circuitry further comprises the step of providing the reset circuitry so that the Z flag is not reset if all of the subtraction operations on the two multi-word operands are zero.
 15. The method of executing a machine instruction requiring a comparison of two multi-word operands in a CPU comprising the steps of: performing a subtraction operation on each of the words of the two multi-word operands respectively; and resetting a zero (Z) flag such that a Z flag status is not set if any of the subtraction operations on the two multi-word operands is not zero.
 16. The method of claim 15, further comprising the step of not resetting the Z flag if all of the subtraction operations on the two multi-word operands are zero.
 17. The method of claim 16, wherein the subtraction step further includes the steps of successively subtracting the words of the multi-length operands from the least significant words to the most significant words.
 18. The method of claim 17, further comprising the step of generating a SUB-Z result is generated for each subtraction operation performed by the subtraction circuitry on the words of the multi-word operands.
 19. An apparatus for comparing a first operand and a second operand, wherein the first operand is formed of n words where n is greater than or equal to 1 and the second operand is formed of n words wherein both the first operand is hierarchically arranged from a first operand lowest order word (LSW) to a first operand highest order word (MSW) and wherein the second operand is hierarchically arranged from a second operand lowest order word (LSW) to a second operand highest order word (MSW), comprising: a first means for subtracting the first operand lowest order word from a second operand lowest order word; a second means coupled to the first means for determining if the result of the subtracting (a) is not zero, then clearing a zero (Z) flag such that a Z flag status is not set; a third means coupled to the second means for determining if the result of the subtracting (a) is zero, then set the Z flag such that the Z flag status is set; a fourth means coupled to the third means for subtracting a first operand next higher order word from a second operand next higher order word; and a fifth means coupled to the fourth means for determining if the result of the subtracting (d) is not zero, then clearing the zero (Z) flag such that the Z flag status is not set.
 20. A computer program product for comparing a first operand and a second operand, wherein the first operand is formed of n words where n is greater than or equal to 1 and the second operand is formed of n words wherein both the first operand is hierarchically arranged from a first operand lowest order word (LSW) to a first operand highest order word (MSW) and wherein the second operand is hierarchically arranged from a second operand lowest order word (LSW) to a second operand highest order word (MSW), comprising: computer code for subtracting the first operand lowest order word from a second operand lowest order word; computer code for determining if the result of the subtracting (a) is not zero, then clearing a zero (Z) flag such that a Z flag status is not set; computer code for determining if the result of the subtracting (a) is zero, then setting the Z flag such that the Z flag status is set; computer code for subtracting a first operand next higher order word from a second operand next higher order word; computer code for determining if if the result of the subtracting (d) is not zero, then clearing the zero (Z) flag such that the Z flag status is not set; computer code for repeating (d)-(e) until the first operand highest order word is subtracted from the second operand highest order word; and a computer readable medium for storing the computer program product.
 21. The computer program product as recited in claim 20, wherein the first operand and the second operand are each integers.
 22. The computer program product as recited in claim 21, further comprising computer code for performing a conditional branch operation that is performed by a central processing unit (CPU).
 23. The computer program product as recited in claim 22, wherein the conditional branch is selected from a group testing for any of the following conditions: equal (=); not equal (≠); less than (<); less than or equal (≦); greater than (>); or greater than or equal (≧). 